In the semiconductor industry, devices are fabricated by a number of manufacturing processes, producing structures of an ever-decreasing size. Current demands for high density and performance associated with ultra large scale integration require formation of device features with high precision and uniformity, which in turn necessitate automated process monitoring, including frequent and detailed inspection of specimens during the manufacturing process.
The term “specimen” used in this specification should be expansively construed to cover any kind of wafer, reticle and other structures, combinations and/or parts thereof used for manufacturing semiconductor integrated circuits, magnetic heads, flat panel displays, and other micro-fabricated devices.
The term “inspection” used in this specification should be expansively construed to cover any kind of detection and/or classification of defects in a specimen provided by using non-destructive inspection tools. By way of non-limiting example, the inspection process can include generating an inspection recipe and/or runtime scanning (in a single or in multiple scans), reviewing, measuring and/or other operations provided with regard to the specimen or parts thereof using the same or different inspection tools. Note that, unless specifically stated otherwise, the term “inspection” or its derivatives used in this specification are not limited with respect to resolution or size of inspection area.
A variety of non-destructive inspection tools includes, by way of non-limiting example, scanning electron microscopes, atomic force microscopes, optical inspection tools, etc.
By way of non-limiting example, inspection can employ a two phase “scanning and review” procedure. During the first phase, the surface of a specimen is inspected at high-speed and relatively low-resolution. In the first phase a defect map is produced to show suspected locations on the specimen having high probability of a defect. During the second phase the suspected locations are more thoroughly analyzed. In some cases both phases can be implemented by the same inspection tool, and in some other cases these two phases are implemented by different inspection tools.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on specimens. Effectiveness of inspection can be increased by using design-related information. For example, one of the known approaches is using design-related information to specify hotspots where, in view of design considerations, defects may occur at a higher probability and further inspecting defects related to the hotspots.
Problems of using design-related information in inspection processes have been recognized in the conventional art and various techniques have been developed to provide solutions. For example:
US Patent Application No. 2006/0110042 discloses a pattern matching method including: detecting an edge of a pattern in a pattern image obtained by imaging the pattern; segmenting the detected pattern edge to generate a first segment set consisting of first segments; segmenting a pattern edge on reference data which serves as a reference for evaluating the pattern to generate a second segment set consisting of second segments; combining any of the segments in the first segment set with any of the segments in the second segment set to define a segment pair consisting of first and second segments; calculating the compatibility coefficient between every two segment pairs in the defined segment pairs; defining new segment pairs by narrowing down the defined segment pairs by calculating local consistencies of the defined segment pairs on the basis of the calculated compatibility coefficients and by excluding segment pairs having lower local consistencies; determining an optimum segment pair by repeating the calculating the compatibility coefficient and the defining new segment pairs by narrowing down the segment pairs; calculating a feature quantity of a shift vector that links the first and second segments making up the optimum segment pair; and performing position matching between the pattern image and the reference data on the basis of the calculated feature quantity of the shift vector.
US Patent Application No. US2006/0108524 discloses a dimension measuring SEM system and a circuit pattern evaluating system. Design data and measured data on an image of a resist pattern formed by photolithography are superposed for the minute evaluation of differences between a design pattern defined by the design data and the image of the resist pattern, and one- or two-dimensional geometrical features representing differences between the design pattern and the resist pattern are calculated. In some cases, the shape of the resist pattern differs greatly from the design pattern due to OPE effect (optical proximity effect). To superpose the design data and the measured data on the resist pattern stably and accurately, an exposure simulator calculates a simulated pattern on the basis of photomask data on a photomask for an exposure process and exposure conditions and superposes the simulated pattern and the image of the resist pattern.
US Patent Application No. 2007/0280527 discloses a technique wherein images of areas of a wafer are generated and registered with respect to computer aided design (CAD) data to provide registered images. Defects in the wafer are then detected by comparing the registered images to one another and defect location information is generated in CAD coordinates.
US Patent Application No. 2009/0238443 discloses a method and equipment for performing matching by selectively using some of multiple patterns provided in a predetermined region of design data, and equipment for implementing the method. First matching by using multiple patterns can be provided in a predetermined region of design data and thereafter second matching can be performed by using some of the multiple patterns provided in the predetermined region.
US Patent Application No. 2009/0266985 discloses a technique wherein design data and sample characteristic information corresponding to individual areas on the design data are used to perform an image quality improvement operation to make appropriate improvements on image quality according to sample characteristic corresponding to the individual areas on the image, allowing a high speed area division on the image. Further, the use of a database that stores image information associated with the design data allows for an image quality improvement operation that automatically emphasizes portions of the image that greatly differ from past images of the similar design data.
US Patent Application No. 2012/0212601 discloses a method for measuring critical dimension (CD) including: scanning at least one area of interest of a die to obtain at least one scanned image; aligning the scanned image to at least one designed layout pattern to identify a plurality of borders within the scanned image; and averaging distances each measured from the border or the plurality of borders of a pattern associated with a specific type of CD corresponding to the designed layout pattern to obtain a value of CD of the die. The value of critical dimensions of dies can be obtained from the scanned image with lower resolution which is obtained by relatively higher scanning speed, so the above-mentioned method can obtain value of CD for every die within entire wafer to monitor the uniformity of the semiconductor manufacturing process within an acceptable inspection time.
US Patent Application No. 2013/204569 discloses a system for generating calibration information usable for wafer inspection, the system including: (I) a displacement analysis module, configured to: (a) calculate a displacement for each target out of multiple targets selected in multiple scanned frames which are included in a scanned area of the wafer, the calculating based on a correlation of: (i) an image associated with the respective target which was obtained during a scanning of the wafer, and (ii) design data corresponding to the image; and (b) determining a displacement for each of the multiple scanned frames, the determining based on the displacements calculated for multiple targets in the respective scanned frame; and (II) a subsequent processing module, configured to generate calibration information including the displacements determined for the multiple scanned frames, and a target database that includes target image and location information of each target of a group of database targets.
US Patent Application 2013/202187 discloses a system for location based wafer analysis, the system comprising: a first input interface configured to obtain: (a) calibration information that includes displacements of multiple frames included in a wafer area of a reference wafer, and (b) a target database that includes a target image and location information for each out of multiple targets in each of the multiple frames; a second input interface, configured to obtain scanning image data of a scan of an inspected area of an inspected wafer; a correlator, configured to: (a) define for each out of multiple targets of the database a search window, based on the displacement of the frame in which the target is included; (b) calculate for each out of multiple targets a run-time displacement, based on a correlation of the target image of the target to at least a portion of an area of the scanned image which is defined by the corresponding search window; and (c) determine a frame run-time displacement for each of multiple run-time frames scanned, based on the target run-time displacements determined for multiple targets in the respective run-time frame; and a processor, configured to generate inspection results for the inspected wafer, with the help of at least one of the frame run-time displacements.
U.S. Pat. No. 7,684,609 discloses several embodiments of a method for reviewing a potential defect on a substrate. In one of the embodiments the method includes obtaining an electron-beam image of a relatively large field of view containing a first image segment. The first image segment is substantially smaller than the field of view and includes a location of the potential defect. A comparison image segment within the field of view is determined. The comparison image segment is transformably identical to the first image segment.